[ A STOIC JOURNEY INTO OPEN SILICON ]

>> TRANSMISSION FROM MENTOR

Hi Bana — I'm Deyaa, a Firmware Engineer and president of the Jordan RISC-V Community.

I want to walk you through a Stoic journey — one where every obstacle is a lesson, every register a puzzle, and every blinking cursor a small victory. We are going to build real hardware, write real firmware, and contribute real code to the open-source world.

By the end of 8 weeks you will have done something most engineers never do: understand a production-grade open chip from gates to OS._

>> TARGET: OPENTITAN

OpenTitan is a fully open Root-of-Trust SoC — hardware, software, and build system all open and production-ready. Built around the LowRISC Ibex RISC-V core, a production-grade RV32IMC processor used in real silicon today.

  • Verified hardware — formal verification, simulation, silicon-proven
  • Full software support — DIFs, firmware libraries, test infrastructure
  • Fully integrated build system — FuseSoC + Bazel + Meson
  • Super modular — vendor any IP, strip what you don't need, add what you do
  • Production grade — shipping in Google's Titan security chips
  • TileLink-UL bus fabric — every peripheral speaks the same language
>> LOADING OBJECTIVES...
Production-grade open hardware
Hardware-accelerated cryptography
RISC-V ecosystem
TileLink bus fabric
Real-Time Operating Systems
FPGA prototyping
Firmware in C
HW vs SW production standards
JTAG debugging
Hardware-software intersection
Device Function Interfaces (DIFs)
Zephyr device tree + Kconfig
>> REQUIRED READING
📁 /materials
OpenTitan Documentation — opentitan.org/book
Ibex RISC-V Core Documentation — ibex-core.readthedocs.io
The Zephyr OS Book — docs.zephyrproject.org
TileLink Specification — sifive.com/tilelink
>> 8-WEEK CURRICULUM [CLICK TO EXPAND]
WEEK 01 Orientation — What Are We Building? +
  • What is OpenTitan — architecture, history, why it exists
  • Repository exploration — understanding the folder structure
  • Set up Verilator simulation — run hello world on the existing SoC
  • What is a TileLink bus and why it matters
  • First dummy test — see your first UART output in simulation
WEEK 02 Building Your Own SoC +
  • LowRISC vendoring mechanism — how to pull IPs into your design
  • TileLink crossbar — how devices connect to the bus
  • Address map — how firmware finds its peripherals
  • Read one reg_pkg.sv — understand register offsets
  • Run your first code on YOUR custom SoC
WEEK 03 Integrating New IP Into Your SoC +
  • Vendor one new IP (GPIO or timer) — full process end to end
  • Wire it into the crossbar and address map
  • Confirm it appears at the right address in simulation
  • Read the UART documentation — understand how a driver is born
  • What is a Device Function Interface (DIF)?
WEEK 04 Bootloader + JTAG Debugging +
  • Boot sequence — what happens from reset to main()
  • Linker script — why it exists and what it controls
  • Write a simple bootloader — load image from SPI flash to SRAM
  • Enable JTAG debugging — watch GDB talk to real hardware
  • Set a breakpoint in bare-metal firmware — feel the power
WEEK 05 Understanding Drivers +
  • Trace one register write — from C code to hardware bit
  • Read an existing DIF — understand the abstraction contract
  • Write a bare-metal driver for the IP you added in week 3
  • Interrupt-driven vs polling — understand the trade-off
  • Test your driver in Verilator simulation
WEEK 06 Running Zephyr OS On Your SoC +
  • What is a real-time OS versus bare-metal — the real difference
  • Device tree — how Zephyr describes hardware in DTS files
  • Kconfig + CMake — how a Zephyr image is configured and built
  • Run Zephyr on your SoC in Verilator simulation
  • Trace a Zephyr driver from DTS node all the way to a register write
WEEK 07 What Is Missing — Finding The Gap +
  • Survey what OpenTitan IPs have Zephyr drivers today
  • Identify the gap — AES, HMAC, CSRNG, GPIO have no drivers
  • Understand Zephyr's PSA Crypto API — the right home for crypto drivers
  • Write your first DIF — software abstraction for one OpenTitan IP
  • Plan your upstream contribution — what will you submit?
WEEK 08 Contributing — Ship It +
  • Write the DT binding for your chosen IP
  • Write the minimal Zephyr driver — DT node to register write
  • Open a pull request to Zephyr upstream
  • Go through code review — respond, iterate, improve
  • Your name in the Zephyr commit log forever
>> MENTORSHIP PROTOCOL
💬
Communication
Direct channel — async first, sync when needed
📋
Meeting Minutes
Google Docs — every session documented
📊
Task Tracking
Linear dashboard — weekly goals, visible progress
⚡
Code Review
GitHub repo — every commit reviewed, feedback given
> This is an open-source inspired process. Everything is transparent, everything is documented, everything ships.
>> STACK
RISC-V OpenTitan Ibex TileLink Zephyr RTOS Verilator SystemVerilog C Firmware JTAG / GDB FIDO2 PSA Crypto FuseSoC FPGA Sky130